The present disclosure relates to semiconductor structures, and particularly to extremely thin semiconductor-on-insulator (ETSOI) field effect transistors having low external resistance, and methods of manufacturing the same.
Extremely thin semiconductor-on-insulator (ETSOI) devices have been proposed to enable continued scaling of complementary metal-oxide-semiconductor (CMOS) devices with superior short channel characteristics at sub-20 nm gate lengths so that enhanced gate control can be provided to a thin semiconductor channel having a thickness not greater than 30 nm. However, high external resistance, i.e., high source/drain resistance, adversely impacts the performance of ETSOI field effect transistor by limiting the on-current. This problem is caused by the limited thickness of a top semiconductor layer, as well as by dopant leaching from the extension regions into a buried oxide layer. In order to enhance the performance of ETSOI field effect transistors, the external resistance of the source and drain regions of the ETSOI field effect transistors need to be minimized.